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航天用SRAM型FPGA抗單粒子翻轉(zhuǎn)設(shè)計(jì)

SEU-tolerant design of SRAM FPGA for space use

  • 摘要: 采用SRAM工藝的FPGA因其性能優(yōu)異，在空間領(lǐng)域的應(yīng)用受到重視；但是在空間環(huán)境中，SRAM型FPGA易受單粒子翻轉(zhuǎn)的影響而導(dǎo)致邏輯故障或功能中斷。文章提出對該類芯片的配置邏輯部分采用回讀比較后刷新、對其BRAM部分采用通用自糾錯(cuò)宏的抗單粒子翻轉(zhuǎn)（SEU）設(shè)計(jì)方案，在犧牲一定的器件性能的情況下，能達(dá)到較好的抗輻射效果。

     

    Abstract: SRAM FPGA is increasingly important in space use because of its excellent performance. In the space environment, however, SRAM FPGA is vulnerable to single event upsets (SEUs), which may lead to logic faults or function interrupts. This paper proposes an SEU-tolerant design by using scrubbing after read-back comparison for the configuration logic part, and using self-correction macro for the BRAM part. This approach is shown to have satisfactory hardening effect against SEUs.

     

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